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Minimizing die fracture in three-dimensional IC

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XYALIS, in collaboration with Mosis, has published an article about “Minimizing die fracture in three-dimensional IC advanced packaging wafer thinning process by inserting polyimide patterns”. This result has been presented in the SPIE Advanced Lithography + Patterning, San Jose, California, …

Single-pass frame generation for multi-layer 3D circuits

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XYALIS, in collaboration with ST Microelectronics,  has published an article about a new methodology to automatically build a single-pass frame for multi-layer 3D circuits.This new methodology uses our frame generation tool GOTframe. This result has been presented in the SPIE Photomask …

Design Driven Dummy Filling

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XYALIS has set up a new methodology to allow an efficient design driven dummy filling technique. It is used in our dummy filling tool GOTstyle. The result has been presented in a paper during the 2021 International Symposium on Electrical, Electronics …

Reducing stress effects on multi-project-wafer reticles

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Collaborating with MOSIS by using GOTmuch and GOTfiller, XYALIS has set up a new methodology to MPW yield and control CPI. The result has been presented in a paper during the SPIE Advanced Lithography online conference, California, USA, 22-26 february …

Large dies stitching: A Technical and Cross-Functional Teams Challenge

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Philippe Morey, Frederic Brault, Eric Beisser, Farid BenzakourXYALIS – Grenoble – FranceConference: SPIE Photomask Technology + EUV Lithography, 2019, Monterey, California, United States ABSTRACT This paper addresses large dies stitching challenges. Stitching is a way to combine several shots ”stitched …



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