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Minimizing die fracture in 3DIC die integration

XYALIS, in collaboration with Mosis, has published a new article in the Journal of Micro/Nanopatterning, Materials, and Metrology about “Minimizing die fracture in 3DIC die integration”. The demand for high-performance semiconductor products has led to reduced wafer feature size, lowered …

XYALIS unveils Hartroid: A Strategic Initiative to Counter Hardware Trojans in Defense Systems

Grenoble, December 18th 2023XYALIS is proud to announce, under the European Union Defence Fund, the start of the Hartroid project. Hartroid stands for “Hardware Trojans Identification in Large-Scale integrated circuits”. Hartroid will develop a solution to detect Hardware Trojans (HT) …

XYALIS at JEVeC conference 2023 in Japan

XYALIS will be present at the JEVeC 2023 Day (Japan EDA Venture Liaison Committee) in Kawasaki, November 27th, 2023. We will present our solution for frame generation step that plays a critical role in mask data preparation flow. Abstract Frame …

XYALIS at SPIE Photomask conference 2023

XYALIS celebrates 25 years of providing state-of-the-art software solutions that increase productivity and reliability of Mask Data Preparation (MDP). With tools ranging from Multi Project Wafer (MPW) placement, frame generation, mask set design, field stitching, mask order form generation, chip …

XYALIS at DAC conference 2023 : booth #2455

XYALIS celebrates 25 years of providing state-of-the-art software solutions that increase productivity and reliability of Mask Data Preparation (MDP). With tools ranging from Multi Project Wafer (MPW) placement, frame generation, mask set design, field stitching, mask order form generation, chip …



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