Minimizing die fracture in 3DIC die integration

XYALIS, in collaboration with Mosis, has published a new article in the Journal of Micro/Nanopatterning, Materials, and Metrology about “Minimizing die fracture in 3DIC die integration”.

The demand for high-performance semiconductor products has led to reduced wafer feature size, lowered package size, and an ever-thinner die for advanced three-dimensional (3D) packaging. Dies down to a thickness of 5 um have been demonstrated. One significant barrier is the fragility of the thin dies, their overall thin form factor, and their impact on yield, reliability, and costs.

We explore the current state of the art in the current crack stop and outline the shortcomings moving forward for stacked 3D integrated circuits (3DIC).

Using a theoretical understanding of fracture mechanics and the new biomimetic concept adapted from nature, we show the implementation of the new crack stop insertions in the die frame for a next-generation 3DIC product.

The proposed crack stop can be easily inserted in the die frame with electronic design automation (EDA) tools using a Python interpreter and has the capability to arrest a crack near its initiation point.

3D crack-stop structure

We show the feasibility of the implementation through EDA tools and outline the next step.

ACM Reference Format:
From The MOSIS Service (California, United States): Jaime Bravo, Lifu Chang, Joshua Zusman
From XYALIS (France): Philippe Morey-Chaisemartin, Eric Beisser, Frederic Brault, Jimmy Lefevre
“Minimizing die fracture in 3DIC die integration”, Journal of Micro/Nanopatterning, Materials, and Metrology 23(1), 011003 – https://doi.org/10.1117/1.JMM.23.1.011003

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