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Minimizing die fracture in three-dimensional IC

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XYALIS, in collaboration with Mosis, has published an article about “Minimizing die fracture in three-dimensional IC advanced packaging wafer thinning process by inserting polyimide patterns”. This result has been presented in the SPIE Advanced Lithography + Patterning, San Jose, California, …

Single-pass frame generation for multi-layer 3D circuits

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XYALIS, in collaboration with ST Microelectronics, ¬†has published an article about a new methodology¬†to automatically build a single-pass frame for multi-layer 3D circuits.This new methodology uses our frame generation tool GOTframe. This result has been presented in the SPIE Photomask …

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