European MEDEA+ CRYSTAL Project: “DFM Photomasks inputs for E...
Resources, white papers, articles
1 XYALIS sarl., 5 place R. Schuman, BP 1510, 38025 Grenoble cedex 01, France
2 Toppan Photomasks France SAS, 118 av. Francis Perrin, 13106 Rousset cedex, France
3 Atmel Rousset SAS, av. Olivier Perroy, 13106 Rousset cedex, France
4Satin IP Technologies SAS, Cap Omega, CS 39521, 34960 Montpellier, France
5 CEA/LETI, 17, Rue des Martyrs 38054 Grenoble, France
The cost of production of a photomask set has been soaring over the last few years, and now reaches $1 million to $2 million, almost 10% of the overall cost of a new project development. And new projects have seen their profitability life-time reduced over time to 3 to 6 months. Any uncontrolled increase in cost or delay can make the difference between a profitable or non profitable project, and can even lead to the cancellation of the entire project. For the last few years, silicon manufacturability issues have been taken into account in the design process through a widespread use of Design For Manufacturing tools, but so far the impact of design on mask manufacturability has not been thoroughly studied. This article presents a novel Design For Mask Manufacturing approach, which defines a robust process encompassing design rules and constraints, validation procedures, exchange mechanisms between all actors in the flow (designers, mask shops, and foundry) in order to minimize the number and impact of mask design issues, to trace their root causes and severity, and automation of the handoff of design and administrative data to the mask shop. A demonstrator for the DFMM flow is being shown.
Keywords: Photomasks, DFM, Cost, Cycle Time, Mask Data preparation, CAD flow
Chip development today is based on shorter lifecycles in a context of more competitive environments and less forgiving technology than ever before. Whereas product complexity and density continue to increase, average selling prices and margins continue to shrink. The cost of a photomask set usually reaches a dollar value of $1 million for the 65nm node to $2 million for the 45nm node . Problems that increase the length or number of design cycles, or mistakes that cause additional re-spins of a die can make the difference between profit and loss for a new product or even result in project cancellation. Knowing that the global cost for a new project is now around $20-$25 million , photomasks manufacturing costs represent almost 10% of a project global cost.
For decades, lithography has been one of the key technologies enabling continuous productivity improvement in the semiconductor industry. One key lesson learnt from the MEDEA+ Stresa symposium  is that every day counts in an industry, which requires huge investments and high returns on investment, so perfectly matching the popular adage “Time is Money”. In addition, the extremely steep yield ramp up required by the market place leave less and less opportunity for redesigning a product as its profitability lifetime is 3-6 months maximum.
As the adoption of immersion techniques is the only way to extend 193 nm lithography down to the 32 nm node, the photomask technology is even more stressed by new challenges related to design interaction, molecular contamination induced by high illumination energy and qualification cycle time induced by Reticule Enhancement Technology (RET) complexity. These issues are high detractors for unplanned cycle time excursions, although they are not linked to a poor technology control. In fact they strongly depend upon interactions of design, process, and arrangement of photomasks throughout the supply chain.
Evolution and today’s status
The DFM concept
The main goal of Design for Manufacturing (DFM) is to increase the yield of the silicon manufacturing process, allowing designers to deal with the increasing complexity of design and manufacturing, to optimize the tradeoff between design and process costs, layout density, chip performance and power consumption, wafer yield and manufacturing risks. DFM is a concept that has been applied for years to various industries, and it was introduced to the semiconductor industry around 1995 .
The importance of DFM in relation to silicon manufacturability has been widely acknowledged in recent years and has been highlighted in many articles and white papers   . Lithography is one key area of concern and numerous RET and Optical Proximity Correction (OPC) models have been developed. Tools are now widely available and fully integrated in the EDA design flow, making silicon process DFM a reality. But so far little work has gone into modeling photomask rules and constraints. Actually, while traditional Design Rule Checkers (DRCs) have evolved into sophisticated and pro-active DFM tool suites, Mask Rule Checkers (MRCs) are still being confined to the final phase of the project, when the GDSII data is released. At this stage RET/OPC further restrict the possibility to revise the design or even to take into account the mask manufacturability issues for a further design cycle. This adds to the fact that most designs are already late .
In short, through several discussions with EDA providers (Mentor Graphics, Cadence, Synopsys, Xyalis…) private discussions with professionals in recent symposiums (Date07 in Nice, Medea+ DAC in Grenoble, and Stresa in Italy), and Mask/Lithography recent symposiums we may conclude that there is no existing comprehensive Photomask DFM flow in place, even if some partial Photomask DFM approaches have already been studied  .
The Photomask impact
Despite the fact that, for consumer products, 100% test coverage is almost never reached due to prohibitive costs, photomasks are required to reach zero defects. With such a constraint, the control of the mask fabrication process must reach the same quality level as required by high safety equipments. While the qualification phase of such a product (medical equipments, plane control systems…) is very long, the full production cycle of a photomask must not go over a few days: including the fabrication itself as well as all controls and measurements. This challenge necessitates a very powerful production control system. All mask shops have already setup such an environment and it is interesting to consider the different levels of implementation of such a production control system.
In the whole silicon chip production process, mask fabrication is often considered as a standalone task. As a clearly contained and independent task, the problem is much simpler to handle. All data and parameters are under the responsibility of the mask supplier and classical production control methods can be applied.
If we now consider the mask fabrication step as part of the whole chip production process, problems become more complex. The number of interactions between the different actors at each step of the process increases dramatically. In this case a much more complex production control system is required, which highly enhances the efficiency of the design and production process as a whole. The impact of such a system in terms of cost and time savings is obvious. This methodology requires that all parameters which can interact with the mask production step be clearly identified. The relationship between the different tasks and their respective parameters is bidirectional. That implies forecast procedures and feedback loops.
In the following chapter we will describe in detail all the constraints that must be taken into account to build a robust process control environment based on this global approach.
The Project and the goals
MEDEA+ is an industry-initiated pan-European Program for advanced co-operative Research and Development in Microelectronics. It has been set up and labeled to ensure Europe’s continued technological and industrial competitiveness in this sector . MEDEA+ started in January 2001 and focuses on “system innovation on silicon”.
The CRYSTAL project consortium involves complementary skills such as design and manufacturing of advanced logic, mixed-signal devices, non-volatile memory, and RF semiconductors (ATMEL), photomask research and development, and manufacturing capabilities (Toppan Photomasks), management, verification, and quality management of Intellectual Property modules (IPs) (Satin IP), micro- and nano- technologies, advanced lithography research laboratories (CEA/LETI), software development dedicated to advanced DFM issues, such as Chemo-Mechanical Polishing modeling and corrections, and Mask Data Preparation operations (XYALIS). Partners already proved their capability to efficiently drive such cooperative R&D projects during MUSCLE , a previous MEDEA+ project, from which several important results will be reused in the present work.
The CRYSTAL project is not directly dedicated to photomask technology enhancement, but focuses on two major challenges: decreasing the cycle time excursions of the lithography supply chain and simplifying photomasks qualification procedure. A specific Task Force was dedicated to address this second goal.
Regarding the first goal, initial studies have led the consortium to focus primarily on the eradication of two root causes of cycle time excursions:
At least 10 to 15% of IC designs induce mask manufacturability issues and time required to fix these issues exponentially increases with mask RET/OPC growing complexity from just a few hours in the past to days (as one run of data preparation routinely takes more 10 hours with databases exceeding 10GB). When an issue cannot be fixed, a waiver specification or a redesign becomes necessary. In most cases it is decided to waive the fix, creating a potential yield burden in an environment where steep yield must be achieved within a few weeks.
The risk of induced contamination damage for 193 nm lithography is 10 to 20 times higher than for 248 nm and requires immediate mask maintenance, costly monitoring, higher cost for double mask. It creates a high risk of erratic cycle time and additional cost. For instance, recent studies by KLA Tencor and Toshiba have estimated the cost of additional inspection between $3 and $7 million for a 15,000 WPM FAB at 193nm. Indirect photomask inspection on wafer also induces productivity loss with use of additional lithographic tools. Short life time means mandatory mask maintenance, double mask set, or mask unavailability linked to cost, delivery, and productivity issues.
The DFM Photomasks Task Force is dedicated to the eradication of the first root cause. By improving device introduction reliability, the innovative Design for Mask Manufacturing concept (DFMM) should contribute up to 40% of the project first goal.
There is also a specific Task Force which is in charge of the second root cause.
Methodology and development
The initial task of the partners has been to perform a large scale analysis of photomask issues. A photomask DFM issue is defined as the case, when the standard manufacturing process of a photomask has to be stopped. To be started again, the manufacturing process requires an internal or external engineering action related to data design. To drive data analysis, a first set of critical geometries has been identified with respect to the limitations of photomask shape inspection, defined by the capability of lithography tools and the limitations of the development and etching process. Then 15 different types of patterns have been identified and included into a MRC software developed by Toppan Photomasks.
Results derived from the manufacturing of more than 10,000 photomasks, processed either at mature or advanced sites, have been retrieved and analyzed. During this extensive study, 1,300 design-related errors have been found, according to the previously-defined critical geometry set. This study has shown that there is no significant statistical difference between mature and advanced technology sites. It has shown that the same type of error keeps being repeated over time. This is pointing out that DFMM suffers from incomplete understanding, wrong practices, missing procedures, or lack of adequate tools at some point in the design process. When two parties do not communicate, one basic question is: do they speak the same language?
Fig. 1. Statistical rule violations, based on more than 10’000 photomasks production – Mature sites vs. Advanced sites
All photomask errors found during inspection do not have the same impact on the final product, depending on the area where they are located. This leads to a conceptual need for Mask Data Ranking (MDR) that could be more precisely developed for each of the three main areas of a photomasks: 70% of errors are located within lettering, titles, and logos areas 14% are located in frame and scribes areas, and only 14% are located within the main dies areas.
At this step we can see that most of the violations come from non active geometries, which are not impacting the wafer performance. Using two types of MDR, one addressing the circuit functionality and the other the mask manufacturability, could help remove the “wrong habits” still in place during mask processing and guarantee chip functionality. If known, automatic waivers could be issued for defects found on non critical patterns, which would not impact mask functionality and cycle time. At the same time, most violations could easily be removed from design databases if an efficient feed-back loop between mask makers and designers were being implemented. Such issues could be flagged during the design process and repaired before mask assembly to prevent any mask stop during manufacturing process in order to gain time.
Rules and Constraints
We have developed an initial set of Rules & Constraints, i.e. information related to photomask issues or limitations that can likely be linked, influenced, or corrected during design. Starting with an approach similar to existing MRCs we have extended the set of rules and constraints in order to add priority management and rules structure definition and we have expanded the scope of data collection to include the chip finishing step, which includes RET operations such as OPC, the mask data preparation step, which includes mask topology design, frame generation, and fiducial patterns placement and generation, the mask manufacturing process itself and the wafer lithography process. This extension allows us to consider the photomask manufacturing process both as an independent industrial process as well as a part of the comprehensive semiconductor industrial process.
Different concurrent structures are used for further transversal analysis. A first level is dedicated to the error severity level, which represents the increasing risk of having to re-spin the photomask instead of successfully fixing the issue. The lower priority level corresponds to cases for which no additional rework is needed; in that case only a waiver between the designer and the mask shop is used to keep trace of the identified potential issue, often located within a non-functional area, such as metal-fill, lettering, logo, title, or frame pattern.
A second structure is used to keep track of error causes, including Rules & Constraints (R&C) violations linked to design optical geometries, R&C violations linked to design root causes, R&C violations linked to design location on the photomask, R&C violations linked to photomask process limitations, R&C violations linked to Place & Route (distinct of location on the photomask such as Multi Project Wafer specific rules, chromium density linearity along reticle, ESD issues…), R&C violations linked to design intent  in main die, R&C violations linked to Lithography / Optics laws / advanced process (including local and macro density uniformity, OPC limitations, stepper illumination strategy, design preferential direction, bi-refringence…).
The DFMM flow
The first version of the standard DFMM flow is based on the approach developed for Rules & Constraints discrimination. This flow has to put in place DFM tests and controls at the end of every principal design step (cell design, design, Place & Route, design finishing, mask data preparation, fabrication), using a share database between internal and external partners. This database uses mask manufacturing inputs collected during the entire mask process.
Fig. 2. DFMM Flow and Decisions made by Supply Chain
The main problems inducing mask delivery delays come from unresolved or distorted geometries, which stop the standard inspection flow and require an alternative process with customer waivers inquiries. This is unnecessary cycle time. To solve this issue a close loop between partners, customers, and vendors must be put in place.
The DFMM strategy requires to build a common DFMM database, shared by IC designers, IC makers and mask shops. All 3 parties that contribute to the mask supply chain own and/or create some information that contribute to the DFMM database. This solution requires that all 3 partners share a standard DFMM data description language to practically exchange the knowledge between partners. Reusing existing results from a previous collaboration , the rules, once validated through the full process, will be communicated to the design group using a standard communication language, such as XML. So that all partners speak the same language, a semantic has to be strictly defined. A list of keywords is defined and definitions are added to each keyword, as it is the case with a SEMI standard. For instance, a clear width feature will be noted as <CLEAR_WIDTH> and its definition will be “glass space width between two adjacent geometries”.
At this step, especially if we consider the photomask flow as a part of the global IC manufacturing flow, it appears that standardization of both the supply chain data exchange format and DFMM rules are critical. This is clearly recommended and accepted by the industry .
Traceability of each step of the photomask manufacturing process is a primary concept, especially for DFM issues, which occur during the cycle. In order to correctly feed the DFMM rule database and the knowledge base related to photomask DFM issues, a formal trace of waivers should be kept including: references of contacts involved, such as mask shop inspection technician, mask data preparation team technician, eventually designer and FAB contacts if they were involved in the waiver, and all related technical data (SEM pictures, AIMS pictures, measurement values…). We selected XML SEMI P10 Certificate of Conformity (CofC or ‘MaskResult’ structure), as the base of formal exchanges between actors.
The methodology that has been discussed in the previous chapters has been implemented by the different partners of the project. This implementation required the setup of verification tools, data exchange mechanisms, and validation procedures.
The validation tools
Considering or not the mask fabrication process as part of a whole process, it is important to carefully check the incoming materials. These materials can be either “hard” materials such as blanks or handling boxes, or “soft” materials such as the design database or the mask order request. The “hard” materials are well identified and are in limited number. A standard input inspection procedure can be easily setup.
The real issue is on the “soft” materials. They are the variable part of the process. Additionally, they often are the most “human” dependent parameter of the whole process. When looking at the statistical results of the study performed at the beginning of the project, it is obvious that the quality of the input data must be carefully checked.
We have identified 4 kinds of tools to efficiently handle the control on the input data:
- design description analysis,
- mask order request validation,
- consistency between technical and administrative data,
- qualification procedure supervisor.
Regarding design description analysis, a layout database analyzer is used. This checker analyzes the consistency of the full database as well as any potential issue regarding mask fabrication. This covers both the detection of unexpected topologies that may cause issues during writing or inspection (such as acute angles) and the detection of unspecified features of the description language being used. The two most often used description languages for design database are GDSII and OASIS. And neither GDSII nor OASIS specifies the behavior of the writing machine when self intersecting polygons or folded path are found in the database. The layout database analyzer identifies this type of issues.
Though mask order requests can be of any format, the SEMI-P10 standard description language (see next chapter) is now widely adopted by the industry. The reliable process control developed as part of this project provides an automatic entry procedure based on the SEMI-P10 format. This procedure extracts and checks all requested data for mask manufacturing.
Considering the fact that we have two external sources of data for mask fabrication, it is mandatory to check their consistency. Specific checking procedures have been setup to warrant the consistency between technical data (design database) and administrative data (mask request). This includes for example the exact size of the die to be written on the mask.
Finally, all these checks must be controlled by a global supervision system. This has been implemented by the adoption of a WEB based validation system for which all the checking rules have been specifically developed. For example, it ensures that the design database and the mask order request are up to date in case of any change by the customer. It also ensures that all the checks have been done on the database and in case of any potential issue, clearly highlights the identified areas.
Data exchange flow
Traceability is key for production process control. This implies that all relevant information be archived in a convenient format, and information exchange between the different actors of the process be possible.
Regarding data storage, a relational database has been setup. It is a SQL database using Oracle. Its contents include, all technical and administrative information received or established during the mask fabrication process, but also all exchanges between the mask shop and their interfaces (designer or foundry). For example, all waivers are archived in relation with each mask and of course with the corresponding release of the related die.
Regarding data exchange, despite the fact that the SEMI-P10 standard has been released a couple of years ago, its usage has not yet been adopted by everyone, especially small design centers. This may be due to the complexity of the description language, which defines almost 1000 keywords. We have introduced a subset of this language , which covers all identified mask process control needs and slightly simplifies the language. All exchanges between the different actors of the whole process are made through this format. This avoids any human intervention or interpretation and greatly improves the reliability of the global flow.
The current project will only be terminated at the end of 2010. We have setup an intermediate demonstrator, using an initial subset of rules, as well as a traceability flow and CAD flow that were used as a proof of concept. The demonstrator was completed in November 2008 and presented at the European Nanoelectronics Forum Paris, December 2nd, 2008.
Based on a VIP Lane server, as the engine for rule monitoring and assessment, and running from a server located in the Satin IP facilities in Montpellier, the demonstrator has highlighted parts of the future DFMM loop. The selected subset of 6 DFMM rules identified for the purpose of the demonstrator has been imported into VIP Lane via its dedicated Graphical User Interface. Automatic assessment of the rules was implemented by linking them to XYALIS EDA tools (GTcheck, a layout database analyzer; GTstyle, a smart CMP metal fill generator; GTarc, a Multi Project Wafer assembly checker). Such links make use of the Xyalis generated log files, as well as of the VIP Lane data mining capabilities. A first library of DFMM rules in XML format has been generated in XML with the VIP Lane export features. The DFMM validation loop has been demonstrated on a set of real designs provided by ATMEL and several test case designs provided by XYALIS, and the results have been displayed through the VIP Lane dynamic dashboards.
Fig. 3. DFMM data standard Supply Chain and Quality Check
The initial results of the project demonstrate the validity of a specific approach for building a dedicated DFMM loop.
The further steps of the project, in 2009 and 2010, will lead from the initial proof of concept demonstrator to the comprehensive DFMM loop. Already defined in the project outlines, several tasks are planned such as: formalization of the standard XML format for the rules, development of a standard Mask Order Form application that can handle both supply chain data and photomask DFM issue traceability, setup of standard procedures for photomask DFM rule quality checks, definition of comprehensive DFMM rules.
The project will also include a full demonstrator, including the manufacturing of several photomasks with and without DFMM rules for comparison, integration of the DFMM loop into an existing design flow and DFMM rules data exchanges between the supply chain flow and world class EDA tools. Final results will be available at the beginning of 2011 and will be developed in a further article.
Weber, C.M., Berglund, C.N., Gabella, P., “Mask Cost and Profitability in Photomask Manufacturing: An Empirical Analysis,” IEEE Transactions on semiconductor manufacturing, Vol. 19 (4), 465-474 (2006).
Weekley, J., “Modeling Total Cost of Ownership for Semiconductor IP,” http://www.design-reuse.com, art. 9065, (2004)
Coll., “MEDEA+ Design Automation Conference 2002”, October 23-25 (2002)
Preston White, K., Jr., Athay, R.N., Trybula. W.J., “Applying DFM in the semiconductor industry,” Electronics Manufacturing Technology Symposium, 438-441 (1995)
Sawicki, J.D., “DFM: magic bullet or marketing hype?,” Proc. SPIE 5379, 1-9 (2004).
Carballo, J., Zorian, Y., Camposano, R., Strojwas, A.J., Kibarian, J.K., Wassung, D., Alexanian, A., Wigley, S., Kelly, N., “DFM Drives Changes in Design Flow”, Design & Test of Computers, IEEE volume 22, Issue 3 (2005)
Smayling, M.C., “DFM – It’s all about Flexibility,” EDP conference (2007)
Laurent, T., “Design Complexity Challenges & Applications Impacts,” SAME keynote session (2006)
Driessen, F. A. J. M, Westra, J., Scheffer, M., Kawakami, K., Tsujimoto, E, M. Yamaji, T. Kawashima, N. Hayashi,.“DFM: design-aware flexible mask-defect analysis”, Proc. SPIE 6730 (2007)
Buck, P., Gladhill, R., Straub, J., “DFM Verification Using Automated Reticle MRC,” Semiconductor International, Vol 29 (6), 73-80, (2006)
Saunier, C., “L’évolution du secteur de la micro/nanoélectronique,” Rapport de l’Assemblée Nationale, 471 (2008).
Torsy, A., “MEDEA+ project 2T302 MUSCLE: masks through user’s supply chain: leadership by excellence,” Proc SPIE 6792, (2008).
Kato, K., Endo, M., Inoue, T., Yamabe, M. , “Mask data rank (MDR) and its application,” 24th European Mask and Lithography Conference. Proc SPIE 6792, (2008)
Farrel, T., “DFM: A Foundry Perspective on the Need for Standards,” Si2 and FSA Open DFM Workshop (2006)