Highlights of XYALIS tools in Kalray design flow



Kalray, a French startup has developed an advanced array processor including 256 cores. This chip has been designed using TSMC 28nm process.

Combining huge designs with complex process rules as lead to a bottleneck regarding layout finishing.

Typically, dummies generation became a real issue as the final database includes both analog parts, which require dedicated dummy filling procedures, and large digital areas with timing and race conditions constraints.

Thanks to their performances and their flexibility, XYALIS tools were successfully used to achieve this complex task.

GTstyle, the dummy filling engine, allowed to fully customize the dummies generation for the analog parts in order to fulfill all designer requirements as well as 28nm design rules.

For example, it was possible to automatically generate mirrored dummies on user-defined windows for highly critical parts.

It took only a couple of days to setup the DRC compliant procedures fully driven by designer constraints.

Dedicated procedures provided by the foundry didn’t allow such a customization.

On the other hand, XYALIS is the exclusive distributor of SmartMRC, an advanced Mask Rule Checker developed by SIINT (Japan), for Europe and USA.

This tool was used onto the final database to detect any line interruption in upper metal layers.

This kind of defect on some power lines can’t be seen as DRC errors but may lead to power drop failures on the chip.

Thanks to advanced features of SmartMRC, checking procedures were setup and allowed to perform a quick validation of the whole power grid of the chip.

Finally, GTcheck was used for final database qualification and GTlabel was used for generating DRC and mask compliant text and labels.

Typically, GTcheck has pointed out some off grid coordinates that may lead to mask writing issues.


  • TSMC 28nm
  • 8 metal layers


  • 3 billion transistors
  • 3 cm2
  • analog + digital parts
  • database (GDS2) : 35 Gb

Tools & Applications


Application : dummy filling

Reasons for using GTstyle :

Feature or capability Goal
Automatic mirroring of dummy cells around a predefined axis in critical areas (of any shape) Guarantee perfect parasitics balancing in high sensitivity paired designs
Mix of different dummy cells for a given layer Fine filling adjustment in small areas
Instantiation of cells (not just layers) Simultaneous generation of poly and active dummy layers
Non orthogonal placement of dummy cells Better parasitics distribution on long wires to avoid race condition issues
Metal dummies stacking (automatic interconnection with vias) Reduce number of uncontrolled floating parasitic capacitors
Optimized generated database Keep a « reasonable » GDS2 file size

Highlights of XYALIS tools in Kalray design flow

Example of metal dummies, along a non orthogonal grid, self-aligned (Meti / Meti-1) with via dummies

Performances & Remarks

  • Current version of GTsyle use one single processor. Run time for dummies generation on a single metal level for the 35Gb database was about 4h. In order to reduce global runtime, the different layers were processed in parallel on different CPUs.
  • Next version of GTstyle will automatically manage this parallelism in order to dramatically reduce memory usage by sharing common data between all processes.
  • Database size increase was less than 10% of original size after generation of all dummies


Application :
Database integrity checking, consistency verification, information extraction

Reasons for using GTcheck :

Feature or capability Goal
Extract layers information Guarantee that all and only expected layers are present in the database
Check « unexpected » polygons Insure that the database doesn’t contain any polygons for which resulting shape is unspecified in GDSII standard, such as self-intersecting polygons, negative steppings in arrays, negative magnification factors, folded paths…
Check off grid coordinates Avoid any rounding issue that may lead to a mask writing defect


Performances & Remarks

  • GTcheck runs on 1 single CPU and takes about 20mn to make the full check onto the 35Gb database.
  • GTcheck is not a DRC, so detected errors such as off grid coordinates may be false errors as they may vanished when merging polygons. Nevertheless, butting polygons drawn onto off grid coordinates, at different levels of the hierarchy have been detected and may have led to mask writing errors due to rounding errors during fracturing.
  • GTcheck is used at major IDM companies as a sign-off tool for database acceptance.

SmartMRC (from SIINT)

Application : 
Basically, a Mask Rule Checker able to detect any unexpected geometric configuration

Reasons for using SmartMRC :

Feature or capability Goal
Easy detection of face to face extremities of rectangular polygons Detect unexpected interruptions in power lines. Not seen by DRC if interruption is larger than min spacing. Not seen by LVS in case of a power grid implementation
Computation of the number of vias instantiated at each power grid intersections Guarantee that all expected vias are present and prevent from power drop failures


Performances & Remarks

  • SmartMRC takes about 20mn to detect all metal line interruptions for each layer of the power grid
  • All detected « errors » were manually checked to verify that they were intentionally designed for power switching features
  • SmartMRC is in use at major worldwide Maskshop for database acceptance.

SmartMRC Mask Rule Checker - error Detection


Miscellaneous tools

GTmerge : merging of multiple GDS2 (merge of separate dummies files)

GTlayer : extraction and/or removal of specified layers

GTlabel : quick and easy identification of cells and versions, including special fonts such as barcodes or OCR compliant fonts

GTlabel - Highlights of XYALIS tools in Kalray design flow

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