Layout finishing of a 28nm, 3 billions transistors and multi-core...

Philippe Morey, Eric Beisser
XYALIS – Grenoble – France
Conference: Photomask and NGL Mask Technology, June, 2013, Yokohama, Japan

ABSTRACT

Designing a fully new 256 cores processor is a great challenge for a fabless startup. In addition to all architecture, functionalities and timing issues, the layout by itself is a bottleneck due to all the process constraints of a 28nm technology. As developers of advanced layout finishing solutions, we were involved in the design flow of this huge chip with its 3 billions transistors. We had to face the issue of dummy patterns instantiation with respect to design constraints. All the design rules to generate the “dummies” are clearly defined in the Design Rule Manual, and some automatic procedures are provided by the foundry itself, but these routines don’t take care of the designer requests.

Such a chip, embeds both digital parts and analog modules for clock and power management. These two different type of designs have each their own set of constraints. In both cases, the insertion of dummies should not introduce unexpected variations leading to malfunctions. For example, on digital parts were signal race conditions are critical on long wires or bus, introduction of uncontrolled parasitic along these nets are highly critical. For analog devices such as high frequency and high sensitivity comparators, the exact symmetry of the two parts of a current mirror generator should be guaranteed. Thanks to the easily customizable features of our dummies insertion tool, we were able to configure it in order to meet all the designer requirements as well as the process constraints. This paper will present all these advanced key features as well as the layout tricks used to fulfill all requirements.

CONSTRAINTS

When performing the layout of any chip, the main set of constraints come from the foundry according to the process specifications. Every constraint is described in the Design Rule Manual. For a 28nm process, many constraints should be met for dummy geometries insertion. We have first, local constraints based on design rules such as spacing and sizes of drawn patterns. This implies that dummy patterns should carefully meet specifications about their shape (width, height, area, aspect ratio…). We then have intra layer density constraints. These constraints may be quite complex:

• global density constraint at chip level
• local density constraint within a window
• density variation between adjacent windows[1]

In each case, constraints are made of a minimum and a maximum value.

At 28nm node, some inter layer density constraints also start to appear. They will certainly become a key point in future technology nodes (22nm and beyond). With these constraints, not only density constraints should be met for a given process layer, but average densities across multiple layers should be met. As an example, layer 1 and layer 2 should reach a density between 30% and 80%, but the average density of layer 1 and 2 should not exceed 70%. Additionally, it seems that the size of the windows on which these constraints should be met, may vary depending on the layer. Hopefully, we didn’t have to face such complex constraints in our case, but this has led to work on new features for the next generation of the dummies insertion engine.

In addition to all these constraints, we have to take into account some spacing or exclusion rules with specific layers which may be physical or virtual. We were also faced with a combination of geometrical constraints and density constraints. The goal was to instantiate two types of dummy patterns, “small” ones at a given distance of active geometries, and “big” ones at another distance (generally larger). We also had to reach a given density of polysilicon as well as a given density of transistors. This implies to identify and manage separately some specific structures. It is important to notice that all process constraints are mandatory. They are all specified in a design rule manual and checked by a DRC. Our goal was to have a 100% error free layout without any waiver.

Design constraints

In all nowadays System On Chip, we have both digital and analog parts. The design constraints will differ depending on the block type. Obviously, the impact of the dummies on the design should be as low as possible in both cases, but we will have specific constraints. The multi-processor array chip, with its 256 cores embed a huge amount of digital blocks, but also many analog blocks for power management, clock control, input/output interfaces, etc…[3]

Regarding analog blocks, we often found symmetrical devices to build high sensitivity comparators or amplifiers. The schematics of such functions are made of 2 identical branches but the layout by itself is drawn with two strictly symmetrical branches. Any difference between the two branches may lead to dramatic results in terms of performances of the full function. In this case, all additional device, including parasitic ones, should be placed in the same way in both branches. It is then important to first identify the areas on which such placement of dummy geometries is required, and then to have a tool able to handle such constraints.

Regarding digital blocks, usually the core by itself is dense enough in lower levels to meet density constraints, and it is generally impossible to add any extra geometries at these levels inside digital blocks. The problem occurs between digital blocks or at upper interconnection layers where we mostly find busses. The signals running on these busses are subject to race conditions. It is important to have all the bits of the data transferred by such interconnection arriving at the same time[7]. This problem is fixed during the synthesis phase of the design and by the Place & Route tool when detailed timing conditions are specified. But once the dummy patterns have been inserted, many parasitics capacitors are”randomly” added and may lead to critical delays on wires. It is then, important to address this issue during dummies instantiation and keep a parasitic balancing on the interconnection wires.

Another request from the designers was the possibility to interconnect the dummies. This allows to make a better model of the parasitic devices: one large capacitor is much more easier to simulate than thousands of small ones, especially if they are grounded.

Workflow constraints

According to previous constraints, it is important for the designer to have a tool that could be easily customizable. Most of the flows provided by foundries are made to meet all process constraints but can’t be modified by the designer, so that all the above mentioned issues can’t be fixed automatically. In this case, insertion of dummies should be made manually in critical cases. This implies, first that the tool can easily take into account all the process constraints, and then can be easily configured by the designer to take into account his constraint while sill meeting process rules.

Another issue of the design CAD flow, is the size and complexity of the data. Designing a 3 billion transistors System On Chip implies huge data bases. This means that the engine used for dummy patterns instantiation should be able to handle many giga bytes of data within the shortest possible time. Some iterations are expected because it may not be possible to reach the density target on the first run: following the local design rules may not allow to place enough dummy structures. It is not acceptable for the designer to spend days to converge on this layout step.

Finally, the last challenge was about the final database size. Starting with a 40Gb layout database, will often lead to a more than 100Gb database with the dummies. This becomes unacceptable. It is important to optimize the resulting database in order to get the smallest possible size. This may save a lot of time for further operations such as DRC and at least data transfer.

DUMMY PATTERNS INSERTION SOLUTIONS

A dedicated engine

A commercial dedicated tool for dummies insertion was available for years and successfully used on “older” technology nodes: 65nm and 45nm. The challenge was to check how it can meet the requirements of a 28nm process with the complexity of a very big design. The tool basically provides all the features requested in the above mentioned constraints. It has been carefully parameterized to fulfill all the foundry specifications. Specific options have been used to follow the designer expectations. For digital blocks and race condition issues on long wires, a dedicated option allows to instantiate the dummy patterns on non orthogonal grids.

The dummy geometries, by themselves, are placed without any rotation, but two contiguous dummy patterns are placed with a slight horizontal and/or vertical shift. This allows a better repartition of the induced parasitics capacitors. In case of orthogonally placed dummies, you may find a full row of dummies placed closely to one wire, while another wire may be far from next row of dummies. Thanks to non orthogonal placement, the average distance between dummy geometries (i.e. parasitic capacitors) is almost the same for all wires.