Single-pass frame generation for multi-layer 3D circuits


XYALIS, in collaboration with ST Microelectronics,  has published an article about a new methodology to automatically build a single-pass frame for multi-layer 3D circuits.
This new methodology uses our frame generation tool GOTframe.

This result has been presented in the SPIE Photomask Technology Conference, Monterey, California, USA, September 26-29, 2022.


This paper presents a novel approach to automatically build frames for 3D chips. These chips may be obtained by stacking multiple dies, but are more often made by a backside wafer processing. This proposed flow works in a single pass and is based on a dedicated constraint-satisfaction software. In addition to the standard placement rules, the different types of constraints used for 3D frames are clearly identified: alignment, overlapping, mirroring. The method to generate separate frames is described. Results and performance obtained in production, for frames involving two different manufacturing processes for wafer front and backside, are detailed.

Access to the abstract

ACM Reference Format:
Authors: Frederic Brault, Philippe Morey, Samuel Boret, Benedicte Bry, Ghislaine Castel, Antonio Marques, Julien Rouessard, and Christelle Segur.
“Single-pass frame generation for multi-layer 3D circuits”, Proc. SPIE 12293, Photomask Technology 2022, 122930Q (1 December 2022); https://doi.org/10.1117/12.2641690

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