Yield optimization through MLR techniques


Some chip manufacturing steps lead to non-negligible process variation at wafer level. Typically, chemo-mechanical planarization, known as CMP, is a non-homogeneous process and thickness variations can be measured depending on the distance from a specific die to the wafer center. These variations have an impact on chip performances and thus on the final yield. This effect may be amplified by the fact that thickness variations on processed wafers introduce focus issues during later photo-lithography steps. Original chip layouts are modified by inserting dummies to correct thickness variation issues due to CMP, but these correction are based on models only depending on average values. In this paper, we propose a methodology to replace a single instance of the field written on the mask by multiple instances of this field as commonly used for Multi Layer Reticles. In the described methodology, each field of a same mask does not consist in different layers of the same chip, but of an optimized image of the same layer of the chip.

European MEDEA+ CRYSTAL Project: “DFM Photomasks inputs for EDA workflow” Task Force


Eric Beisser1, Michel Tissier2, David Au3, Stéphane Bonniol4, Patrick Garcia3,Philippe Morey-Chaisemartin1, Dominique Sadran2, Isabelle Servin5, Michel Tabusse4 1 XYALIS sarl., 5 place R. Schuman, BP 1510, 38025 Grenoble cedex 01, France2 Toppan Photomasks France SAS, 118 av. Francis Perrin, 13106 …

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