CMP Monitoring and Prediction Based Metal Fill


Nowadays, two different methodologies are used to address the CMP issues. On one hand, we find basic design oriented methods consisting of reaching a minimal density of geometries in the design. On the other hand we find model based approaches in which complex process related parameters are used. This makes these techniques, either not accurate or not usable by designers. In both cases there is no efficient monitoring of the CMP effect through Process Control Modules.
This paper presents a new methodology to improve CMP process yield from the designer side. A prediction function of metal thickness variations due to CMP is established thanks to specific test structures. A method to monitor the CMP process evolution at no cost is presented and finally a technique for using the prediction function to drive metal filling procedure is described.



At XYALIS, we are very concern by the words used by the EDA industry. A misunderstanding between actors in this industry may have tremendous consequences.
As we are also pioneers by the tools we develop and used in the fields of mask data preparation and metal fill, we enrich this glossary every time is needed.
Remarks and propositions are welcomed.

Yield optimization through MLR techniques


Some chip manufacturing steps lead to non-negligible process variation at wafer level. Typically, chemo-mechanical planarization, known as CMP, is a non-homogeneous process and thickness variations can be measured depending on the distance from a specific die to the wafer center. These variations have an impact on chip performances and thus on the final yield. This effect may be amplified by the fact that thickness variations on processed wafers introduce focus issues during later photo-lithography steps. Original chip layouts are modified by inserting dummies to correct thickness variation issues due to CMP, but these correction are based on models only depending on average values. In this paper, we propose a methodology to replace a single instance of the field written on the mask by multiple instances of this field as commonly used for Multi Layer Reticles. In the described methodology, each field of a same mask does not consist in different layers of the same chip, but of an optimized image of the same layer of the chip.

European MEDEA+ CRYSTAL Project: “DFM Photomasks inputs for EDA workflow” Task Force


Eric Beisser1, Michel Tissier2, David Au3, Stéphane Bonniol4, Patrick Garcia3,Philippe Morey-Chaisemartin1, Dominique Sadran2, Isabelle Servin5, Michel Tabusse4 1 XYALIS sarl., 5 place R. Schuman, BP 1510, 38025 Grenoble cedex 01, France2 Toppan Photomasks France SAS, 118 av. Francis Perrin, 13106 …



It’s a banality to say that nowadays, databases for digital chips are more than huge. The physical description of an SOC, encoded in the classical GDSII format, now often goes over 20Gbytes. Files of up to 200Gbytes have been reported by mask houses.

Even if storage systems and data transfer links can handle such sizes, it is obvious that so big files are difficult to manipulate.

GDSII was introduced by Calma in 1978 as a successor of GDS format created in 1971. Since almost 30 years, no major change have been made to this de-facto standard while chips complexity was multiplied by 105 to 106.
In addition to file size issue, numerical values needed to describe geometries of nanoscale structures on 300mm wafers will soon reach the 32 bits limits of GDSII format.

With concerns to such problems, OASIS format was developed and its first official specification was released in 2004 [1].

This article, shortly describes how size and precision limitation issues are managed in OASIS format. It also point out some critical points of this format and finally gives some tricks to really get full benefits from OASIS.
This article is based on the extensive experience of Xyalis on GDSII manipulation software and will show how to use its new OASIS capabilities to circumvent potential pitfall and problem using this new standard.

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