Layout finishing of a 28nm, 3 billions transistors and multi-core processor


Philippe Morey, Eric BeisserXYALIS – Grenoble – FranceConference: Photomask and NGL Mask Technology, June, 2013, Yokohama, Japan ABSTRACT Designing a fully new 256 cores processor is a great challenge for a fabless startup. In addition to all architecture, functionalities and …

Using a Mask Rule Checker as an Electrical Rule Checker


Philippe Morey, Eric BeisserXYALIS – Grenoble – FranceConference: Photomask and NGL Mask Technology, June, 2013, Yokohama, Japan ABSTRACT Design complexity sometimes grows faster than EDA tools performances, and some innovation should be made on the design flow to guarantee the …

Highlights of XYALIS tools in Kalray design flow


Context Kalray, a French startup has developed an advanced array processor including 256 cores. This chip has been designed using TSMC 28nm process. Combining huge designs with complex process rules as lead to a bottleneck regarding layout finishing. Typically, dummies …

Industry needs analysis for developing new skills in nano-electronics


NanoSkills[Nan, 2012] is a project belonging to Leonardo program and sponsored by EACEA[EAC, 2012]. Its is developed by a consortium of both universities and SMEs. The role of the the universities is to develop online courses on nanoelectronics while the SMEs will help to setup a professional environment and to validate it. The goal of the project is to provide master level courses to both students and employees. The content of the courses should bring the learners, the skills expected by the industry to work on the most advanced topics of nano-electronics. In order to fulfill the industry needs, a preliminary analysis has been performed among the various customers. This paper describes this analysis. We will fist detail the elaboration of the questionnaire. We will then review the answers, and finally analyze the results in order to select the most important courses to be developed.

CMP Monitoring and Prediction Based Metal Fill


Nowadays, two different methodologies are used to address the CMP issues. On one hand, we find basic design oriented methods consisting of reaching a minimal density of geometries in the design. On the other hand we find model based approaches in which complex process related parameters are used. This makes these techniques, either not accurate or not usable by designers. In both cases there is no efficient monitoring of the CMP effect through Process Control Modules.
This paper presents a new methodology to improve CMP process yield from the designer side. A prediction function of metal thickness variations due to CMP is established thanks to specific test structures. A method to monitor the CMP process evolution at no cost is presented and finally a technique for using the prediction function to drive metal filling procedure is described.

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